1、功能说明
     1、ATIM1_CH2门控ATIM1_CH1和GTIMA3_CH1, GTIMA3_CH1门控GTIMA4_CH1

2、使用环境
    软件开发环境：KEIL MDK-ARM V5.34
    软件开发环境：IAR EWARM 8.50.1

    芯片支持：
        N32H730  
        N32H735   
        N32H735EC
        N32H760
        N32H762
        N32H765
        N32H765EC
        N32H785
        N32H785EC
        N32H787

3、使用说明
    系统配置；
        1、时钟源：HSI+PLL
        2、系统时钟频率：
			M7核: 600MHz
        3、端口配置：
			PA8选择为ATIM1_CH1输出
			PA9选择为ATIM1_CH2输入
			PB6选择为GTIMA3_CH1输出
			PA0选择为GTIMA4_CH1输出	
        4、TIM：
			ATIM1_CH2门控ATIM1_CH1和GTIMA3_CH1, GTIMA3_CH1门控GTIMA4_CH1

    使用方法：
        1、编译后打开调试模式，用示波器或者逻辑分析仪观察ATIM1_CH1,GTIMA3_CH1,GTIMA4_CH1的波形
        2、ATIM1_CH2高电平定时器开始计数，低电平停止

4、注意事项
   主定时器的时钟需要大于等于从定时器
   默认情况下，开发板的PA9和PA10跳线帽连接到NSLINK的虚拟串行端口。如果PA9和PA10未用作项目中的串行端口，而是用于其他用途，则必须拔掉串行端口跳线帽。
    
1. Function description
     1. ATIM1_CH2 gated ATIM1_CH1 and GTIMA3_CH1, GTIMA3_CH1 gated GTIMA4_CH1

2. Development environment
    Software development environment: KEIL MDK-ARM V5.34
    Software development environment: IAR EWARM 8.50.1

    Supported chips:
        N32H730  
        N32H735   
        N32H735EC
        N32H760
        N32H762
        N32H765
        N32H765EC
        N32H785
        N32H785EC
        N32H787

3. How to use
   System Configuration:
        1. Clock source: HSI+PLL
        2. System Clock frequency: 
            M7 Core:     600MHz
        3. Port configuration:
			PA8 is selected as ATIM1_CH1 output
			PA9 is selected as ATIM1_CH2 output
			PB6 is selected as GTIMA3_CH1 output
			PA0 is selected as GTIMA4_CH1 output
        4. TIM:
			ATIM1_CH2 gated ATIM1_CH1 and GTIMA3_CH1, GTIMA3_CH1 gated GTIMA4_CH1
     Instructions:
         1. After compiling, turn on the debug mode, use an oscilloscope or logic analyzer to observe the waveforms of ATIM1_CH1, GTIMA3_CH1, GTIMA4_CH1
         2. ATIM1_CH2 high level timer starts counting, low level stops
4. Attention
    The clock of the master timer needs to be greater than or equal to that of the slave timer.
    By default, the PA9 and PA10 jumper caps of the development board are connected to the virtual serial port of NSLINK. If PA9 and PA10 are not used as serial ports in the project, and are used for other purposes, the serial port jumper caps must be unplugged.

